In dynamic semiconductor memory storage devices it is essential that storage node capacitor cell plates be large enough to retain an adequate charge or capacitance in spite of parasitic capacitances and noise that may be present during circuit operation. As is the case for most semiconductor integrated circuitry, circuit density is continuing to increase at a fairly constant rate. The issue of maintaining storage node capacitance is particularly important as the density of DRAM arrays continue to increase for future generations of memory devices.
The ability to densely pack storage cells while maintaining required storage capabilities is a crucial requirement of semiconductor manufacturing technologies if future generations of expanded memory array devices are to be successfully manufactured.
One method of maintaining, as well as increasing, storage node size in densely packed memory devices is through the use of "stacked storage cell" design. With this technology, two layers of a conductive material such as polycrystalline silicon (polysilicon or poly) are deposited over an access device on a silicon wafer with dielectric layers sandwiched between each poly layer. A cell constructed in this manner is known as a stacked capacitor cell (STC). Such a cell utilizes the space over the access device for capacitor plates, has a low soft error rate (SER) and may be used in conjunction with interplate insulative layers having a high dielectric constant.
However, it is difficult to obtain sufficient storage capacitance with a conventional STC capacitor as the storage electrode area is confined within the limits of its own cell area. Also, maintaining good dielectric breakdown characteristics between poly layers in the STC capacitor becomes a major concern once insulator thickness is appropriately scaled.
A paper submitted by H. Arima et al., entitled "A NOVEL STACKED CAPACITOR CELL WITH DUAL CELL PLATE FOR 64Mb DRAMs," IEDM, Dig. Tech. Papers, pp. 651-654, 1990, herein incorporated by reference, discusses a stacked capacitor with dual cell plates (DCP).
The DCP structure and its development is shown in FIGS. 2a-f, pp. 652 of the article mentioned previously. The storage node is developed by two polysilicon layers which forms a rectangular box shaped poly structure. Capacitor dielectric film surrounds the surface of the rectangular poly structure and is then covered with poly layer that creates the upper cell plate to complete the storage capacitor cell. This process takes a total of four photo mask steps; two photo steps to open the buried contacts and delineate the poly buffer layer (as in FIG. 2a), one photo step to reopen the buried contact once the surface has been coated with oxide that is planarized followed by depositions of poly, cell dielectric, and poly respectively (as shown in FIG. 2c), and one photo step to pattern the storage node plate (as shown in FIG. 2e).
The present invention further develops an existing stacked capacitor fabrication process to construct a more advanced three-dimensional stacked capacitor cell than that of the DCP and requires only a total of two photomask steps.